VHDL generation from SDL speci cations

The aim of this paper is to present an approach that allows the generation of VHDL from system level speci cations in SDL. Our approach overcome the main known problem encountered by previous work which is the communication between di erent processes. We allow SDL communication to be translated into VHDL for synthesis. This is made possible by the use of an intermediate form that support a powerful communication model which enable the representation in a synthesis oriented manner of most communication schemes. This intermediate form allows the re nement of the system in order to obtain the desired solution. The main re nement step, called communication synthesis, is aimed at xing the protocol and the interface used by the di erent processes to communicate. The re ned speci cation is translated into VHDL for synthesis using existing CAD tools. We illustrate the feasibility of our approach through two SDL to VHDL translation examples.